Stavros Kalafatis received the BS degree from University of Surrey in 1989 and MS degree from University of Arizona, Tucson in 1991. He is the Associate Department Head and a Professor of Practice in the ECE department at Texas A&M University. He has been the Capstone program director since 2016. Before that he worked for Intel Corp as a Senior Director of R&D in the CPU division.
His research interests are on Datacenter system optimization especially with respect to CPU performance, IO latency and memory subsystem optimization under NVM; Improvements in the area of SDI, SDN, SDS to enable higher server deployment efficiency; Robotic application to manufacturing environments. Ex sanding, loading/unloading, human-robot interaction, swarming to enable complex task completion and Sensor system development as applied to agriculture ex soil analysis, herding of cattle as well as daily task optimizations ex. human movement tracking of heavy loads, applications of drones to security.
Associate Department Head
Department of Electrical and Computer Engineering
Texas A&M University
Contact Information
Office: WEB 205E
Phone: 979-458-8429
Email: skalafatis-tamu@exchange.tamu.edu
Awards & Honors
- Intel Achievement Award (Lynnfield Team), 2005
- Intel Divisional Recognition Award, 1993, 2000, 2001, 2003, 2009, 2010
Education
- MSEE University of Arizona, Tucson, AZ, 1991
- BSEE University of Surrey, Surrey, UK, 1989
For details about open positions in Prof. Kalafatis’ research group:
Send your resume along with a letter stating your research experience and goals to skalafatis-tamu@tamu.edu
Selected Publications
Vrecenar, R., Hall, M., Zshiesche, J., Naidu, M., Rajendran, J., & Kalafatis, S. (2019, November). Red Teaming a Multi-Colored Bluetooth Bulb. In 2019 IEEE 37th International Conference on Computer Design (ICCD) (pp. 293-296). IEEE.
Knudson, Dean, Stavros Kalafatis, Carsten Kleiner, Stephen Zahos, Barbara Seegebarth, Jonas Detterfelt, Iman Avazpour et al. “Global software engineering experience through international capstone project exchanges.” In Proceedings of the 13th International Conference on Global Software Engineering, pp. 54-58. 2018.
Kalafatis, Stavros, et al. “Qualification of event detection by thread ID and thread privilege level.” U.S. Patent No. 7,448,025. 4 Nov. 2008.
Kalafatis, Stavros, Alan B. Kyker, and Robert D. Fisch. “Method and apparatus for thread switching within a multithreaded processor.” U.S. Patent No. 6,535,905. 18 Mar. 2003.
Kalafatis, Stavros, Alan B Kyker, Robert D Fisch. “Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction.” U.S. Patent No. US6971104B2, 29 Nov 2005.
Kalafatis, Stavros, Alan B. Kyker, and Robert D. Fisch. “Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor.” U.S. Patent No. 6,865,740. 8 Mar. 2005.
Kalafatis, Stavros, Alan B. Kyker, and Robert D. Fisch. “Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information.” US Patent No. 6854118. 8 Feb 2005.
Kalafatis, Stavros, Alan B. Kyker, and Robert D. Fisch. “Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition.” US Patent No. 6850961. 1 Feb 2005.
Kalafatis, Stavros, Alan B. Kyker, and Robert D. Fisch. “Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction. ” US Patent No. 6795845, 2004.
Kalafatis, Stavros, Alan B. Kyker, and Robert D. Fisch. “Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread” US Patent No. 6785890, 2004.
Kalafatis, Stavros, Alan B. Kyker, and Robert D. Fisch. “Method and apparatus for thread switching within a multithreaded processor.” US Patent No. 6535905, 2003.
D’sa, R. V., Hebda, R. E., Kalafatis, S., Kyker, A. B., & Chaput, R. B. (2000). U.S. Patent No. 6,151,671. Washington, DC: U.S. Patent and Trademark Office.
D’sa, R. V., Hebda, R. E., Kalafatis, S., Kyker, A. B., & Chaput, R. B. (2002). U.S. Patent No. 6,374,350. Washington, DC: U.S. Patent and Trademark Office.
D’sa, R. V., Kyker, A. B., Sheaffer, G. S., Espinosa, G. P., Kalafatis, S., & Hebda, R. E. (2000). U.S. Patent No. 6,055,630. Washington, DC: U.S. Patent and Trademark Office.
Kalafatis, Stavros. “Dual edge adjusting digital phase-locked loop having one-half reference clock jitter.” U.S. Patent No. 5,546,434. 13 Aug. 1996.
Kalafatis, Stavros, John F. O’Hanlon, and Kenneth P. Gross. “Design and development of a rotating wafer scanner.” Optical Engineering 32.2 (1993): 420-424.
Kalafatis, Stavros. The design and development of an atmospheric and vacuum rotating wafer scanner. Diss. The University of Arizona, 1991.